IEEE International High Level Design
Validation and Test Workshop 2003
November 12-14, 2003, Hyatt Regency Hotel, San Francisco, California
Download PDF Advance Program

FINAL PROGRAM

Wednesday, November 12

  • 5:00-7:30pm Registration
  • 7:30-9:30pm Buffet Reception

Thursday, November 13

  • 7:00-8:00am Continental Breakfast
     
  • 8:15-8:30am Welcoming Remarks
     
  • 8:30-10:15am SESSION 1: Invited Session -- "Nano, Quantum, and Molecular Computing: Challenges in Verification and Test"
    Organizers: Sandeep Shukla, Virginia Tech; Ramesh Karri, Polytechnic Univ.

  • 10:15-10:45am Break
     
  • 10:45-12:00pm SESSION 2: Processor Validation and Test
    Session Chair: Ajit Dingankar, Intel
    1. Software-Based Self-Test Methodology for Crosstalk Faults in Processors
      Xiaoliang Bai, Li Chen, Sujit Dey
    2. FPgen - A Test Generation Framework for Datapath Floating-Point Verification
      Merav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koifman, Raviv Nagel
    3. Piparazzi: A Test Program Generator for Micro-architecture Flow Verification
      Allon Adir, Eyal Bin, Avi Ziv

      4.  
  • 12:00-1:15pm Lunch
     
  • 1:15-2:30pm SESSION 3: High-Level Design Transformations
    Session Chair: Yatin Hoskote, Intel
    1. Automatic Functional Verification of Memory Oriented High Level Source Code Transformations
      K.C. Shashidhar, Maurice Bruynooghe, Francky Catthoor and Gerda Janssens
    2. Refactoring Digital Hardware Designs with Assertion Libraries
      Flavio de Paula, Claudionor Coelho, Harry Foster, Jose Nacif, Joseph Tompkins, Antonio Fernandes, Diogenes da Silva
    3. High-level Optimization of Pipeline Design
      Jennifer P.L. Campbell and Nancy A. Day

      4.  
  • 2:30-3:00pm Break
     
  • 3:00-4:15pm SESSION 4: SAT and Applications
    Session Chair: Ian Harris, UC Irvine
    1. Integrating CNF and BDD Based SAT Solvers
      Sivaram Gopalakrishnan, Vijay Durairaj and Priyank Kalla
    2. Logic Transformation based approach to SAT Solver
      Dhiraj Pradhan
    3. Enhancing SAT-based Equivalence Checking with Static Logic Implications
      Rajat Arora and Michael S. Hsiao

      4.  
  • 4:15-4:45pm Break
     
  • 4:45-6:00pm SESSION 5: System-Level Issues
    Session Chair: Bernard Courtois, TIMA
    1. Relating vehicle-level and network-level reliability through high-level fault injection
      Fulvio Corno, Paolo Gabrielli, Simonluca Tosato
    2. Testing ThumbPod: Softcore Bugs are Hard to Find
      Patrick Schaumont, Kazuo Sakiyama, Yi Fan, David Hwang, Shenglin Yang, Alireza Hodjat, Bocheng Lai, Ingrid Verbauwhede
    3. Verifying LOC Based Functional and Performance Constraints
      Xi Chen and Harry Hsieh, University of California, Riverside Felice Balarin and Yosinori Watanabe, Cadence Berkeley Laboratories

      4.  

Friday, November 14

  • 7:00-8:00am Continental Breakfast
     
  • 8:00-9:40am SESSION 6: Functional Vector Generation and Coverage
    Session Chair: Harry Foster, Jasper Design Automation
    1. Comparison of Bayesian Networks and Data Mining for Coverage Directed Verification
      Markus Braun Wolfgang Rosenstiel Klaus-Dieter Schubert
    2. Enhancing the Control and Efficiency of the Covering Process
      Shai Fine Avi Ziv
    3. Functional Vector Generation for Assertion-Based Verification at Behavioral Level Using Interval Analysis
      I. Ugarte, P. Sanchez
    4. Redundant Functional Faults Reduction by Saboteurs Synthesis
      Franco Fummi, Cristina Marconcini, Graziano Pravadelli

      5.  
  • 9:40-10:10am Break
     
  • 10:10-11:50am SESSION 7: Advances in Sequential Verification
    Session Chair: Rajarshi Mukherjee, Calypto Design Systems
    1. ATPG-based PreImage Computation: Efficient Search Space Pruning With ZBDD
      Kameshwar Chandrasekar and Michael S. Hsiao
    2. BDD-Based Verification of Scalable Designs
      Daniel Große and Rolf Drechsler
    3. Matching in the presence of don't-cares and redundant sequential elements for sequential equivalence checking
      Solaiman Rahim, Bruno Rouzeyre, Lionel Torres
    4. Mathematical Framework for Representing Discrete Functions as Word-level Polynomials
      Dhiraj K. Pradhan, Serkan Askar, Maciej Ciesielski

      5.  
  • 11:50-1:00pm Lunch
     
  • 1:00-1:50pm SESSION 8: Behavioral/System-Level Test Case Generation
    Session Chair: Andrew Piziali, Verisity
    1. High-level test generation for hardware testing and software validation
      O. Goloubeva, M. Sonza Reorda, M. Violante
    2. Scheduling of Transactions in System-Level Test-Case Generation
      Roy Emek, Yehuda Naveh

      3.  
  • 1:50-2:15pm Break
     
  • 2:15-3:30pm SESSION 9: Comparisons and Evaluations
    Session Chair: Michael Hsiao, Virginia Tech
    1. A Comparison of BDDs, BMC, and Sequential SAT for Model Checking.
      G. Parthasarathy M.K Iyer Li-C. Wang K-T.Cheng
    2. Genetic Algorithms: the Philosopher's Stone or an Effective Solution for High-level TPG?
      Alessandro Fin, Franco Fummi
    3. A Method for the Evaluation of Behavioral Fault Models
      Emilio Gaudette, Michael Moussa, Ian G. Harris

      4.  
  • 3:30-4:00pm Break
     
  • 4:00-5:30pm SESSION 10: Panel -- "What's the Next 'Big Thing' in Simulation-Based Verification?"
    Organizers: Moshe Levinger and Avi Ziv, IBM Haifa