HLDVT'04 Call for Papers IEEE International High Level Design Validation and Test Workshop 2004 November 10-12, 2004, The Lodge at Sonoma, Sonoma, California HLDVT 2004 is the ninth in a series of annual workshops designed to bring together a community of researchers in the areas of microelectronic design, verification, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for validating such systems. The workshop provides an informal forum for discussion of substantive issues that cut across diverse areas in system-level design. Major topics include, but are not limited to, the following: High Level Design Validation High Level Design Error Modeling High Level Test Bench Generation Testing Core Based Designs Hardware/Software Co-Testing Simulation-Based Verification Emulation and Prototyping Error Models and Verification Test Hardware/Software Co-Validation High Level DFT/Synthesis for Test High Level ATPG/Fault Simulation Validation of Microprocessors Design Error Debug & Diagnosis Formal Verification Methods On-Chip Software Testing High-Level Performance/Power Models The Program Committee invites authors to submit an extended summary comprising no more than 4 pages (10pt minimum font size, reasonable margins and line spacing) describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please indicate: title, name and affiliations of all authors, and the topic category. Also identify a contact author and provide complete mailing address, phone number, fax number and an e-mail address. Panel proposals are also invited. All submissions must be made electronically in PDF or Postscript format using the paper submission webpage: http://www.hldvt.com/submissions Please ensure that your PDF or Postscript file is readable by Acrobat Reader or Ghostview. Submissions are due no later than 11:59pm Pacific Time, July 7, 2004. Authors will be notified of the disposition of their HLDVT submissions by August 16, 2004. The submission of an extended summary or panel proposal will be considered evidence that upon acceptance, the author(s) will present their paper or organize their panel at the workshop. Authors of accepted papers will have the option of including a camera-ready copy of their manuscript in the formal workshop proceedings published by the IEEE Computer Society press. The final HLDVT manuscript will be due in early September 2004, depending on publishing deadlines. Authors of selected HLDVT submissions will be invited to submit an extended version which will be reviewed for a special issue of ACM Transactions on Design Automation of Electronic Systems on "Design Validation of Large Systems". Extended versions submitted to the ACM special issue will undergo an additional round of reviews before final acceptance in the special issue. Additional information and contact addresses are available at the conference website: http://www.hldvt.com/04 Queries regarding paper submissions and the program can be addressed to the program chair: Ian G. Harris, programchair@hldvt.com. Other queries can be addressed to the general chair: Alan J. Hu, generalchair@hldvt.com. HLDVT 2004 is sponsored by the IEEE Computer Society Test Technology Technical Council and the IEEE Computer Society Design Automation Technical Committee. Organizing Committee General Chair: Alan Hu, U. British Columbia Program Chair: Ian G. Harris, UC Irvine Vice Program Chair: Robert Jones, Intel Past Chair: Masahiro Fujita, U. Tokyo Finance Chair: Wolfgang Rosenstiel, Tuebingen U. Panels Chair: Yatin Hoskote, Intel Publicity Chair: Harry Foster, Jasper Design Systems Publications Chair: Laurent Fournier, IBM Haifa Local Arrangements Chair: Vijay Nagasamy, Crimson Microsystems Electronic Media Chair: Ismet Bayraktaroglu, Sun Microsystems European Liaison: Bernard Courtois, TIMA Asian Liaison: Hiroyuki Tomiyama, Nagoya U. Program Committee Mark Aagaard, U. Waterloo Jacob Abraham, U. Texas, Austin Hussain Al-Asaad, UC Davis Felice Balarin, Cadence Berkeley Labs Mike Bartley, Elixent Ltd Gerard Berry, Esterel Technologies Tim Cheng, UC Santa Barbara Hans Eveking, TU Darmstadt Farzan Fallah, Fujitsu Labs of America Harry Foster, Jasper Design Automation Masahiro Fujita, U. Tokyo Franco Fummi, Univ. di Verona Kiyoharu Hamaguchi, Osaka U. John Hayes, U. Michigan Michael Hsiao, Virginia Tech. Ramesh Karri, Polytechnic U. Yaron Kashai, Verisity Luciano Lavagno, Politecnico di Torino Amitava Majumdar, SUN Microsystems Peter Marwedel, U. Dortmund Rajarshi Mukherjee, Calypto Systems Dhiraj Pradhan, U. Bristol Paolo Prinetto, Politecnico di Torino Sreeranga Rajan, Fujitsu Labs of America Bruno Rouzeyre, LIRMM Juergen Ruf, IBM Daniel Saab, Case Western Reserve U. Patrick Schaumont, UC Los Angeles Sandeep Shukla, Virginia Tech Atsushi Takahara, NTT Li-C. Wang, UC Santa Barbara Jin Yang, Intel Steering Committee Sujit Dey, UC San Diego Alex Orailoglu, UC San Diego Prab Varma, Veritable, Inc.