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In pdf format.
| HLDVT 05 WEDNESDAY, NOVEMBER 30 |
- 5:00 pm - 7:30 pm - Registration
- 7:30 pm - 9:30 pm - Reception & Buffet Dinner
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| THURSDAY, DECEMBER 1 |
- 7:00 am - 8:00 am - Continental Breakfast
- 7:00 am - 6:00 pm - Registration
- 8:00 am - 8:10 am - Welcome Remarks
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Session 1 - 8:10 am - 9:50 am - Test, Fault & Error Modeling
- Simulation-Based Functional Test Generation for Embedded Processors
Hung-Pin (Charles) Wen, opwen@ece.ucsb.edu, Li-C. Wang, Kwang-Ting Cheng, Univ. of California, Santa Barbara, CA
- Scalable Defect Mapping and Configuration of Memory-Based Nanofabrics
Chen He, che@ece.utexas.edu, Univ. of Texas, Freescale Semiconductor, Inc., Austin TX, Margarida F. Jacome, Gustavo de Veciana, Univ. of Texas, Austin, TX
- Improvement of Fault Injection Techniques Based on VHDL Code Modification
Joaquin Gracia, jgracia@disca.upv.es, Daniel Gil, Juan C. Baraza, Pedro J. Gil, Universidad Poltecnica de Valencia, Valencia, Spain
- MVP: A Mutation-Based Validation Paradigm
Jorge Campos, jcampos@ucdavis.edu, Hussain Al-Asaad, Univ. of California, Davis, CA
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9:50 am - 10:10 am - Break |
Session 2 - 10:10 am - 11:25 am - Equivalence Verification
- Establishing Latch Correspondence for Embedded Circuits of PowerPC(R) Microprocessors
Himyanshu Anand, himyanshu.anand@freescale.com, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis, Freescale Semiconductor Inc., Austin, TX
- Sequential Equivalence Checking Based on K-th Invariants and Circuit SAT Solving
Feng Lu, lufeng@ece.ucsb.edu, Tim Cheng, Univ. of California, Santa Barbara, CA
- VERISEC: VERIfying Equivalence of SEquential Circuits using SAT
Manan Syal, mysal@vt.edu, Intel Corp.,Hillsboro, OR, Michael S. Hsiao, Virginia Tech., Blacksburg, VA
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11:25 am - 11:45 am - Break |
Session 3 - 11:45 am - 12:35 pm - System-Level Modeling & Co-Design
- Automated Clock Inference for Stream Function-Based System Level Specifications
Sandeep K. Shukla, shukla@vt.edu, Virginia Tech., Blacksburg, VA, Jean-Pierre Talpin, IRISA/INRIA, Rennes, France
- Cosimulation of ITRON-Based Embedded Software with SystemC
Shin-ichiro Chikada, chikada@ertl.jp, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada, Nagoya Univ., Aichi, Japan
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12:35 pm - 2:00 pm - Lunch |
Session 4 - 2:00 pm - 3:15 pm - Validation Test Generation I
- A Software Test Program Generator for Verifying System-on-Chips
Adriel Cheng, acheng@eleceng.adelaide.edu.au, Atanas Parashkevov, Cheng-Chew Lim, The Univ. of Adelaide, Adelaide, SA, Australia
- Stimulus Generation for Interface Protocol Verification Using the Non-Deterministic Extended Finite State Machine Model
Che-Hua Shih, matar@eda.ee.nctu.edu.tw, Juinn-Dar Huang, Jing-Yang Jou, National Chiao Tung Univ., Hsinchu, Taiwan, ROC
- DVGen: A Test Generator for the Transmeta Efficeon VLIW Processor
Kevin D. Rich, kdrich@transmeta.com, Shankar Govindaraju, Robert Shaw, David Dobrikin, Transmeta Corp., Santa Clara, CA
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3:15 pm - 3:35 pm - Break |
Session 5 - 3:35 pm - 4:25 pm - Validation Test Generation II
- Reuse in System-Level Stimuli-Generation
Shady Copty, shady@il.ibm.com, Itai Jaeger, Yossi Lichtenstein, Yoav Katz, IBM Haifa Research Labs, Haifa, Israel, Anita Devadason, Audrey Romonosky, IBM Corp., Austin, TX
- Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
Ari Frueng, arief@il.ibm.com, Shai Fine, Itai Jaeger, Yehuda Naveh, Avi Ziv, IBM Haifa Research Labs, Haifa, Israel, Yishay Mansour, Tel Aviv Univ., Tel Aviv, Israel
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4:25 pm - 4:45 pm - Break |
Session 6 - 4:45 pm - 6:00 pm - New Approaches in Simulation
- A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal
Qingwei Wu, qiwu@cadence.com, Cadence Design Systems, Inc., San Jose, CA, Michael S. Hsiao, Virginia Tech., Blacksburg, VA
- Validating Families of Latency Insensitive Protocols
Syed Suhaib, ssuhaib@vt.edu, Deepak Mathaikutty, Sandeep Shukla, Virginia Tech., Blacksburg, VA, David Berner, INRIA-IRISA, France
- GASIM: A Fast Galois Field Based Simulator for Functional Model
Ashutosh Kumar Singh, ashutosh@unitar.edu.my, UNITAR, Selangor Darul Ehsan, Malaysia, Dhiraj K. Pradhan, Univ. of Bristol, Bristol, United Kingdom, T.L. Rajaprabhu, Georgia Institute of Tech., Atlanta, GA, Abusaleh M. Jabir, Oxford Brookes Univ., Oxford, United Kingdom
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| FRIDAY, DECEMBER 2 |
- 7:00 am - 12:00 pm - Registration
- 7:00 am - 8:00 am - Continental Breakfast
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Session 7 - 8:00 am - 9:40 am - Formal Verification
- Overlap Reduction in Symbolic System Traversal
Prakash Mohan Perariandam, prakash@informatik.uni-tuebingen.de, P.K. Nalla, R.J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel, Univ. of Teubingen, Tübingen, Germany
- Formal Verification of High-Level Conformance with Symbolic Simulation
Armaghan Naik, armaghan.w.naik@intel.com, Intel Corp., Hudson, MA, Roope Kaivola, Intel Corp., Hillsboro, OR
- A Method for Generation of GSTE Assertion
Graphs Edward Smith, ed.smith@comlab.ox.ac.uk, Oxford Univ., Oxford, United Kingdom
- Automatic Abstraction Refinement for Petri Nets Verification
Zhenyu Chen, zychen@mail.edu.cn, Conghua Zhou, Decheng Ding, Nanjing Univ., China
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9:40 am - 10:00 am - Break |
Session 8 - 10:00 am - 11:15 am - SAT & SAT Applications
- An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging
Chia-Chih Yen, jackr@eda.ee.nctu.edu.tw, Jing-Yang Jou, National Chiao-Tung Univ., Hsinchu, Taiwan
- Increasing the Deductibility in CNF Instances for Efficient SAT-based Bounded Model Checking
Vishnu C. Vimjam, vvimjam@vt.edu, Michael S. Hsiao, Virgina Tech., Blacksburg, VA
- B-Cubing Theory: New Possibilities for Efficient SAT-Solving
Alan J. Hu, ajh@cs.ubc.ca, Domagoj Babic, Jesse Bingham, Univ. of British Columbia, Vancouver, BC, Canada
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11:15 am - 11:35 am - Break |
Session 9 - 11:35 am - 12:25 pm - Security
- Multi-level Design Validation in a Secure Embedded System
David D. Hwang, dhwang@ee.ucla.edu, Shenglin Yang, Ingrid Verbauwhede, Univ. of California, Los Angeles, CA, Patrick Schaumont, Virginia Tech., Blacksburg, VA
- Security Evaluation Against Electromagnetic Analysis at Design Time
Huiyun Li, huiyun.li@cl.cam.ac.uk, Theodore Markettos, Simon Moore, Univ. of Cambridge, Cambridge, United Kingdom
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12:25 pm - 1:45 pm - Lunch |
Session 10 - 1:45 pm - 3:00 pm - Coverage
- Formal Meaning of Coverage Metrics in Simulation-Based Hardware Design Verification
Pablo Sanchez, sanchez@teisa.unican.es, Iņigo Ugarte, Univ. of Cantabria, Cantabria, Spain
- Advanced Analysis Techniques for Cross-Product Coverage
Laurent Fournier, laurent@il.ibm.com, Hezi Aztachi, Avi Ziv, Keren Zohar, IBM Haifa Research Labs, Haifa, Israel
- A Proof of Correctness for the Construction of Property Monitors
Katell Morin-Allory, katell.morin-allory@imag.fr, Dominique Borrione, Tima Labs. Grenoble, Cedex, France
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3:00 pm - 3:20 pm - Break |
Session 11 - 3:20 pm - 5:00 pm - Panel
- Functional Coverage: Is Your Design Exposed?
| Moderator: | | Andrew Piziali - Cadence Design Systems, Verification Application Specialist, Plano, TX |
| Panelists: | |
Neyaz Khan - Cadence Design Systems, Plano, TX
Laurent Fournier - IBM, Haifa, Israel
Gery Osowiecki - Texas Instruments, Plano, TX
Tom Anderson - Synopsys, San Jose, CA
Mike Miller - Intel, Hillsboro, OR |
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