IEEE International High Level Design
Validation and Test Workshop 2007


Final Call for Papers (PDF)
Organizing Committee
General Chair
Michael Hsiao, Virginia Tech
Program Chair
Yatin Hoskote, Intel
Past Chair
Robert Jones, Intel
Finance Chair
Priyank Kalla, Univ. of Utah
Publicity Chair
Ismet Bayraktaroglu, Sun
Local Arrangements Chair
Vijay Nagasamy, NEC Electronics

Program Committee
Mark Aagaard, Univ. of Waterloo
Samar Abdi, UC Irvine
Jacob Abraham, Univ. of Texas
Hussain Al-Asaad, UC Davis
Felice Balarin, Cadence Berkeley Labs
Valeria Bertacco, Univ. of Michigan
Tim Cheng, UC Santa Barbara
Scott Davidson, Sun
Farzan Fallah, Fujitsu Labs of America
Franco Fummi, Univ. di Verona
Kiyoharu Hamaguchi, Osaka Univ.
Ian Harris, UC Irvine
John Hayes, Univ. of Michigan
Harry Hsieh, UC Riverside
Alan Hu, Univ. British Columbia
Michael Kishinevsky, Intel
Ed McCluskey, Stanford Univ.
Alex Orailoglu, UC San Diego
Wolfgang Rosenstiel, T¨ubingen Univ.
Pablo Sanchez, Univ. of Cantabria
Sandeep Shukla, Virginia Tech
Lionel Torres, Univ. of Montpellier
Li-C.Wang, UC Santa Barbara
Jin Yang, Intel
Avi Ziv, IBM

Steering Committee
Bernard Courtois, CMP-TIMA
Sujit Dey, UC San Diego
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Blue Pearl Software

HLDVT 2007 is the twelfth in a series of annual workshops designed to bring together a community of researchers in the areas of design, validation, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum in recent years for researchers and practitioners to discuss the practical issues associated with simulation and validation of extremely large designs. This year, the theme is ”Challenges in multi-core design, validation and test”. Topics of interest include:

  • Simulation-Based Validation
  • Formal Verification
  • Design Abstraction & Behavioral Modeling
  • Error Trace Interpretation & Debugging
  • Hybrid SAT/BDD/ATPG Methods
  • On-Chip and Core-Based Testing
  • Test Generation for Defects, Design Errors, and Delay
  • Design/Synthesis for Test
  • Hardware/Software Co-Validation
  • Emulation and Prototyping
  • Design from abstract specifications

The Program Committee invites authors to submit papers not to exceed 8 pages (10pt minimum font size, reasonable margins and line spacing) describing original and unpublished work. On the title page, please indicate: paper title, name and affiliations of all authors, and the topic category. Also identify a contact author and provide complete mailing address, phone number, fax number and an e-mail address. Panel proposals are also invited. All submissions must be made electronically in PDF or Postscript format using the paper submission webpage: http://www.hldvt.com/submissions

Please ensure that your PDF or Postscript file is readable by Acrobat Reader or Ghostview. The submission of an paper or panel proposal will be considered evidence that upon acceptance, the author(s) will present their paper or organize their panel at the workshop.

Submission deadline: June 16, 2007
Final manuscript: September 13, 2007

Authors of selected HLDVT’07 papers will be invited to submit extended versions for a special issue of a selected IEEE publication, to be published in 2008.

Additional information is available at http://www.hldvt.com/07
Questions regarding paper submissions and the program may be addressed to the program chair: Yatin Hoskote, programchair@hldvt.com. Other questions may be addressed to the general chair: Michael Hsiao, generalchair@hldvt.com.

HLDVT 2007 is sponsored by the IEEE Computer Society Test Technology Technical Council and the IEEE Computer Society Design Automation Technical Committee. HLDVT 2007 receives corporate support from IBM and Intel.